std_detect/detect/arch/
riscv.rs

1//! Run-time feature detection on RISC-V.
2
3features! {
4    @TARGET: riscv;
5    @CFG: any(target_arch = "riscv32", target_arch = "riscv64");
6    @MACRO_NAME: is_riscv_feature_detected;
7    @MACRO_ATTRS:
8    /// A macro to test at *runtime* whether instruction sets are available on
9    /// RISC-V platforms.
10    ///
11    /// RISC-V standard defined the base sets and the extension sets.
12    /// The base sets are RV32I, RV64I, RV32E or RV128I. Any RISC-V platform
13    /// must support one base set and/or multiple extension sets.
14    ///
15    /// Any RISC-V standard instruction sets can be in state of either ratified,
16    /// frozen or draft. The version and status of current standard instruction
17    /// sets can be checked out from preface section of the [ISA manual].
18    ///
19    /// Platform may define and support their own custom instruction sets with
20    /// ISA prefix X. These sets are highly platform specific and should be
21    /// detected with their own platform support crates.
22    ///
23    /// [ISA manual]: https://riscv.org/specifications/ratified/
24    ///
25    /// # Unprivileged Specification
26    ///
27    /// The supported ratified RISC-V instruction sets are as follows:
28    ///
29    /// * RV32E: `"rv32e"`
30    /// * RV32I: `"rv32i"`
31    /// * RV64I: `"rv64i"`
32    /// * A: `"a"`
33    ///   * Zaamo: `"zaamo"`
34    ///   * Zalrsc: `"zalrsc"`
35    /// * B: `"b"`
36    ///   * Zba: `"zba"`
37    ///   * Zbb: `"zbb"`
38    ///   * Zbs: `"zbs"`
39    /// * C: `"c"`
40    ///   * Zca: `"zca"`
41    ///   * Zcd: `"zcd"` (if D is enabled)
42    ///   * Zcf: `"zcf"` (if F is enabled on RV32)
43    /// * D: `"d"`
44    /// * F: `"f"`
45    /// * M: `"m"`
46    /// * Q: `"q"`
47    /// * V: `"v"`
48    ///   * Zve32x: `"zve32x"`
49    ///   * Zve32f: `"zve32f"`
50    ///   * Zve64x: `"zve64x"`
51    ///   * Zve64f: `"zve64f"`
52    ///   * Zve64d: `"zve64d"`
53    /// * Zicboz: `"zicboz"`
54    /// * Zicntr: `"zicntr"`
55    /// * Zicond: `"zicond"`
56    /// * Zicsr: `"zicsr"`
57    /// * Zifencei: `"zifencei"`
58    /// * Zihintntl: `"zihintntl"`
59    /// * Zihintpause: `"zihintpause"`
60    /// * Zihpm: `"zihpm"`
61    /// * Zimop: `"zimop"`
62    /// * Zacas: `"zacas"`
63    /// * Zawrs: `"zawrs"`
64    /// * Zfa: `"zfa"`
65    /// * Zfh: `"zfh"`
66    ///   * Zfhmin: `"zfhmin"`
67    /// * Zfinx: `"zfinx"`
68    /// * Zdinx: `"zdinx"`
69    /// * Zhinx: `"zhinx"`
70    ///   * Zhinxmin: `"zhinxmin"`
71    /// * Zcb: `"zcb"`
72    /// * Zcmop: `"zcmop"`
73    /// * Zbc: `"zbc"`
74    /// * Zbkb: `"zbkb"`
75    /// * Zbkc: `"zbkc"`
76    /// * Zbkx: `"zbkx"`
77    /// * Zk: `"zk"`
78    /// * Zkn: `"zkn"`
79    ///   * Zknd: `"zknd"`
80    ///   * Zkne: `"zkne"`
81    ///   * Zknh: `"zknh"`
82    /// * Zkr: `"zkr"`
83    /// * Zks: `"zks"`
84    ///   * Zksed: `"zksed"`
85    ///   * Zksh: `"zksh"`
86    /// * Zkt: `"zkt"`
87    /// * Zvbb: `"zvbb"`
88    /// * Zvbc: `"zvbc"`
89    /// * Zvfh: `"zvfh"`
90    ///   * Zvfhmin: `"zvfhmin"`
91    /// * Zvkb: `"zvkb"`
92    /// * Zvkg: `"zvkg"`
93    /// * Zvkn: `"zvkn"`
94    ///   * Zvkned: `"zvkned"`
95    ///   * Zvknha: `"zvknha"`
96    ///   * Zvknhb: `"zvknhb"`
97    /// * Zvknc: `"zvknc"`
98    /// * Zvkng: `"zvkng"`
99    /// * Zvks: `"zvks"`
100    ///   * Zvksed: `"zvksed"`
101    ///   * Zvksh: `"zvksh"`
102    /// * Zvksc: `"zvksc"`
103    /// * Zvksg: `"zvksg"`
104    /// * Zvkt: `"zvkt"`
105    /// * Ztso: `"ztso"`
106    ///
107    /// There's also bases and extensions marked as standard instruction set,
108    /// but they are in frozen or draft state. These instruction sets are also
109    /// reserved by this macro and can be detected in the future platforms.
110    ///
111    /// Draft RISC-V instruction sets:
112    ///
113    /// * RV128I: `"rv128i"`
114    /// * J: `"j"`
115    /// * P: `"p"`
116    /// * Zam: `"zam"`
117    ///
118    /// # Performance Hints
119    ///
120    /// The two features below define performance hints for unaligned
121    /// scalar/vector memory accesses, respectively.  If enabled, it denotes that
122    /// corresponding unaligned memory access is reasonably fast.
123    ///
124    /// * `"unaligned-scalar-mem"`
125    /// * `"unaligned-vector-mem"`
126    #[stable(feature = "riscv_ratified", since = "1.78.0")]
127
128    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32i: "rv32i";
129    without cfg check: true;
130    /// RV32I Base Integer Instruction Set
131    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32e: "rv32e";
132    without cfg check: true;
133    /// RV32E Base Integer Instruction Set
134    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv64i: "rv64i";
135    without cfg check: true;
136    /// RV64I Base Integer Instruction Set
137    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv128i: "rv128i";
138    without cfg check: true;
139    /// RV128I Base Integer Instruction Set
140
141    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] unaligned_scalar_mem: "unaligned-scalar-mem";
142    /// Has reasonably performant unaligned scalar
143    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] unaligned_vector_mem: "unaligned-vector-mem";
144    /// Has reasonably performant unaligned vector
145
146    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicsr: "zicsr";
147    without cfg check: true;
148    /// "Zicsr" Extension for Control and Status Register (CSR) Instructions
149    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicntr: "zicntr";
150    without cfg check: true;
151    /// "Zicntr" Extension for Base Counters and Timers
152    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihpm: "zihpm";
153    without cfg check: true;
154    /// "Zihpm" Extension for Hardware Performance Counters
155    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zifencei: "zifencei";
156    without cfg check: true;
157    /// "Zifencei" Extension for Instruction-Fetch Fence
158
159    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihintntl: "zihintntl";
160    without cfg check: true;
161    /// "Zihintntl" Extension for Non-Temporal Locality Hints
162    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihintpause: "zihintpause";
163    without cfg check: true;
164    /// "Zihintpause" Extension for Pause Hint
165    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zimop: "zimop";
166    without cfg check: true;
167    /// "Zimop" Extension for May-Be-Operations
168    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicboz: "zicboz";
169    without cfg check: true;
170    /// "Zicboz" Extension for Cache-Block Zero Instruction
171    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicond: "zicond";
172    without cfg check: true;
173    /// "Zicond" Extension for Integer Conditional Operations
174
175    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] m: "m";
176    /// "M" Extension for Integer Multiplication and Division
177
178    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] a: "a";
179    /// "A" Extension for Atomic Instructions
180    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zalrsc: "zalrsc";
181    /// "Zalrsc" Extension for Load-Reserved/Store-Conditional Instructions
182    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zaamo: "zaamo";
183    /// "Zaamo" Extension for Atomic Memory Operations
184    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zawrs: "zawrs";
185    /// "Zawrs" Extension for Wait-on-Reservation-Set Instructions
186    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zacas: "zacas";
187    /// "Zacas" Extension for Atomic Compare-and-Swap (CAS) Instructions
188    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zam: "zam";
189    without cfg check: true;
190    /// "Zam" Extension for Misaligned Atomics
191    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] ztso: "ztso";
192    without cfg check: true;
193    /// "Ztso" Extension for Total Store Ordering
194
195    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] f: "f";
196    /// "F" Extension for Single-Precision Floating-Point
197    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] d: "d";
198    /// "D" Extension for Double-Precision Floating-Point
199    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] q: "q";
200    without cfg check: true;
201    /// "Q" Extension for Quad-Precision Floating-Point
202    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfh: "zfh";
203    /// "Zfh" Extension for Half-Precision Floating-Point
204    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfhmin: "zfhmin";
205    /// "Zfhmin" Extension for Minimal Half-Precision Floating-Point
206    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfa: "zfa";
207    without cfg check: true;
208    /// "Zfa" Extension for Additional Floating-Point Instructions
209
210    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfinx: "zfinx";
211    /// "Zfinx" Extension for Single-Precision Floating-Point in Integer Registers
212    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zdinx: "zdinx";
213    /// "Zdinx" Extension for Double-Precision Floating-Point in Integer Registers
214    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zhinx: "zhinx";
215    /// "Zhinx" Extension for Half-Precision Floating-Point in Integer Registers
216    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zhinxmin: "zhinxmin";
217    /// "Zhinxmin" Extension for Minimal Half-Precision Floating-Point in Integer Registers
218
219    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] c: "c";
220    /// "C" Extension for Compressed Instructions
221    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zca: "zca";
222    without cfg check: true;
223    /// "Zca" Compressed Instructions excluding Floating-Point Loads/Stores
224    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zcf: "zcf";
225    without cfg check: true;
226    /// "Zcf" Compressed Instructions for Single-Precision Floating-Point Loads/Stores on RV32
227    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zcd: "zcd";
228    without cfg check: true;
229    /// "Zcd" Compressed Instructions for Double-Precision Floating-Point Loads/Stores
230    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zcb: "zcb";
231    without cfg check: true;
232    /// "Zcb" Simple Code-size Saving Compressed Instructions
233    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zcmop: "zcmop";
234    without cfg check: true;
235    /// "Zcmop" Extension for Compressed May-Be-Operations
236
237    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] b: "b";
238    without cfg check: true;
239    /// "B" Extension for Bit Manipulation
240    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zba: "zba";
241    /// "Zba" Extension for Address Generation
242    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbb: "zbb";
243    /// "Zbb" Extension for Basic Bit-Manipulation
244    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbc: "zbc";
245    /// "Zbc" Extension for Carry-less Multiplication
246    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbs: "zbs";
247    /// "Zbs" Extension for Single-Bit Instructions
248
249    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbkb: "zbkb";
250    /// "Zbkb" Extension for Bit-Manipulation for Cryptography
251    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbkc: "zbkc";
252    /// "Zbkc" Extension for Carry-less Multiplication for Cryptography
253    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbkx: "zbkx";
254    /// "Zbkx" Extension for Crossbar Permutations
255    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zknd: "zknd";
256    /// "Zknd" Cryptography Extension for NIST Suite: AES Decryption
257    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zkne: "zkne";
258    /// "Zkne" Cryptography Extension for NIST Suite: AES Encryption
259    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zknh: "zknh";
260    /// "Zknh" Cryptography Extension for NIST Suite: Hash Function Instructions
261    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zksed: "zksed";
262    /// "Zksed" Cryptography Extension for ShangMi Suite: SM4 Block Cipher Instructions
263    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zksh: "zksh";
264    /// "Zksh" Cryptography Extension for ShangMi Suite: SM3 Hash Function Instructions
265    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zkr: "zkr";
266    /// "Zkr" Entropy Source Extension
267    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zkn: "zkn";
268    /// "Zkn" Cryptography Extension for NIST Algorithm Suite
269    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zks: "zks";
270    /// "Zks" Cryptography Extension for ShangMi Algorithm Suite
271    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zk: "zk";
272    /// "Zk" Cryptography Extension for Standard Scalar Cryptography
273    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zkt: "zkt";
274    /// "Zkt" Cryptography Extension for Data Independent Execution Latency
275
276    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] v: "v";
277    /// "V" Extension for Vector Operations
278    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve32x: "zve32x";
279    /// "Zve32x" Vector Extension for Embedded Processors (32-bit+; Integer)
280    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve32f: "zve32f";
281    /// "Zve32f" Vector Extension for Embedded Processors (32-bit+; with Single-Precision Floating-Point)
282    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve64x: "zve64x";
283    /// "Zve64x" Vector Extension for Embedded Processors (64-bit+; Integer)
284    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve64f: "zve64f";
285    /// "Zve64f" Vector Extension for Embedded Processors (64-bit+; with Single-Precision Floating-Point)
286    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve64d: "zve64d";
287    /// "Zve64d" Vector Extension for Embedded Processors (64-bit+; with Double-Precision Floating-Point)
288    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvfh: "zvfh";
289    /// "Zvfh" Vector Extension for Half-Precision Floating-Point
290    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvfhmin: "zvfhmin";
291    /// "Zvfhmin" Vector Extension for Minimal Half-Precision Floating-Point
292
293    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvbb: "zvbb";
294    /// "Zvbb" Extension for Vector Basic Bit-Manipulation
295    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvbc: "zvbc";
296    /// "Zvbc" Extension for Vector Carryless Multiplication
297    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkb: "zvkb";
298    /// "Zvkb" Extension for Vector Cryptography Bit-Manipulation
299    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkg: "zvkg";
300    /// "Zvkg" Cryptography Extension for Vector GCM/GMAC
301    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkned: "zvkned";
302    /// "Zvkned" Cryptography Extension for NIST Suite: Vector AES Block Cipher
303    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvknha: "zvknha";
304    /// "Zvknha" Cryptography Extension for Vector SHA-2 Secure Hash (SHA-256)
305    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvknhb: "zvknhb";
306    /// "Zvknhb" Cryptography Extension for Vector SHA-2 Secure Hash (SHA-256/512)
307    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksed: "zvksed";
308    /// "Zvksed" Cryptography Extension for ShangMi Suite: Vector SM4 Block Cipher
309    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksh: "zvksh";
310    /// "Zvksh" Cryptography Extension for ShangMi Suite: Vector SM3 Secure Hash
311    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkn: "zvkn";
312    /// "Zvkn" Cryptography Extension for NIST Algorithm Suite
313    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvknc: "zvknc";
314    /// "Zvknc" Cryptography Extension for NIST Algorithm Suite with Carryless Multiply
315    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkng: "zvkng";
316    /// "Zvkng" Cryptography Extension for NIST Algorithm Suite with GCM
317    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvks: "zvks";
318    /// "Zvks" Cryptography Extension for ShangMi Algorithm Suite
319    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksc: "zvksc";
320    /// "Zvksc" Cryptography Extension for ShangMi Algorithm Suite with Carryless Multiply
321    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksg: "zvksg";
322    /// "Zvksg" Cryptography Extension for ShangMi Algorithm Suite with GCM
323    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkt: "zvkt";
324    /// "Zvkt" Extension for Vector Data-Independent Execution Latency
325
326    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] j: "j";
327    without cfg check: true;
328    /// "J" Extension for Dynamically Translated Languages
329    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] p: "p";
330    without cfg check: true;
331    /// "P" Extension for Packed-SIMD Instructions
332}
std_detect/detect/arch/riscv.rs

std_detect/detect/arch/
riscv.rs
