Module riscv_shared

Shared RISC-V intrinsics

Missing floating-point register instructions

We are deliberately not providing instructions that could change the floating-point rounding mode or exception behavior or read the accrued exceptions flags: frcsr, fscsr, fsrm, frflags, fsflags.

Rust makes no guarantees whatsoever about the contents of the accrued exceptions register: Rust floating-point operations may or may not result in this register getting updated with exception state, and the register can change between two invocations of this function even when no floating-point operations appear in the source code (since floating-point operations appearing earlier or later can be reordered).

Modifying the rounding mode leads to immediate Undefined Behavior: Rust assumes that the default rounding mode is always set and will optimize accordingly. This even applies when the rounding mode is altered and later reset to its original value without any floating-point operations appearing in the source code between those operations (since floating-point operations appearing earlier or later can be reordered).

If you need to perform some floating-point operations and check whether they raised an exception, use a single inline assembly block for the entire sequence of operations.

If you need to perform some floating-point operations under a differen rounding mode, use a single inline assembly block and make sure to restore the original rounding mode before the end of the block.

Re-exports

pub use p::*;

pub use zb::*;

pub use zk::*;

Modules

p 🔒

RISC-V Packed SIMD intrinsics; shared part.

zb 🔒

zk 🔒

Functions

fence_i^⚠Experimental

Generates the FENCE.I instruction

frrmExperimental

Reads the floating-point rounding mode register frm

hfence_gvma^⚠Experimental

Hypervisor memory management fence for guest physical address and virtual machine

hfence_gvma_all^⚠Experimental

Hypervisor memory management fence for all virtual machines and guest physical addresses

hfence_gvma_gaddr^⚠Experimental

Hypervisor memory management fence for guest physical address

hfence_gvma_vmid^⚠Experimental

Hypervisor memory management fence for given virtual machine

hfence_vvma^⚠Experimental

Hypervisor memory management fence for given guest virtual address and guest address space

hfence_vvma_all^⚠Experimental

Hypervisor memory management fence for all guest address spaces and guest virtual addresses

hfence_vvma_asid^⚠Experimental

Hypervisor memory management fence for given guest address space

hfence_vvma_vaddr^⚠Experimental

Hypervisor memory management fence for given guest virtual address

hinval_gvma^⚠Experimental

Invalidate hypervisor translation cache for guest physical address and virtual machine

hinval_gvma_all^⚠Experimental

Invalidate hypervisor translation cache for all virtual machines and guest physical addresses

hinval_gvma_gaddr^⚠Experimental

Invalidate hypervisor translation cache for guest physical address

hinval_gvma_vmid^⚠Experimental

Invalidate hypervisor translation cache for given virtual machine

hinval_vvma^⚠Experimental

Invalidate hypervisor translation cache for given guest virtual address and guest address space

hinval_vvma_all^⚠Experimental

Invalidate hypervisor translation cache for all guest address spaces and guest virtual addresses

hinval_vvma_asid^⚠Experimental

Invalidate hypervisor translation cache for given guest address space

hinval_vvma_vaddr^⚠Experimental

Invalidate hypervisor translation cache for given guest virtual address

hlv_b^⚠Experimental

Loads virtual machine memory by signed byte integer

hlv_bu^⚠Experimental

Loads virtual machine memory by unsigned byte integer

hlv_h^⚠Experimental

Loads virtual machine memory by signed half integer

hlv_hu^⚠Experimental

Loads virtual machine memory by unsigned half integer

hlv_w^⚠Experimental

Loads virtual machine memory by signed word integer

hlvx_hu^⚠Experimental

Accesses virtual machine instruction by unsigned half integer

hlvx_wu^⚠Experimental

Accesses virtual machine instruction by unsigned word integer

hsv_b^⚠Experimental

Stores virtual machine memory by byte integer

hsv_h^⚠Experimental

Stores virtual machine memory by half integer

hsv_w^⚠Experimental

Stores virtual machine memory by word integer

nopExperimental

Generates the NOP instruction

pauseExperimental

Generates the PAUSE instruction

sfence_inval_ir^⚠Experimental

Generates the SFENCE.INVAL.IR instruction

sfence_vma^⚠Experimental

Supervisor memory management fence for given virtual address and address space

sfence_vma_all^⚠Experimental

Supervisor memory management fence for all address spaces and virtual addresses

sfence_vma_asid^⚠Experimental

Supervisor memory management fence for given address space

sfence_vma_vaddr^⚠Experimental

Supervisor memory management fence for given virtual address

sfence_w_inval^⚠Experimental

Generates the SFENCE.W.INVAL instruction

sinval_vma^⚠Experimental

Invalidate supervisor translation cache for given virtual address and address space

sinval_vma_all^⚠Experimental

Invalidate supervisor translation cache for all address spaces and virtual addresses

sinval_vma_asid^⚠Experimental

Invalidate supervisor translation cache for given address space

sinval_vma_vaddr^⚠Experimental

Invalidate supervisor translation cache for given virtual address

wfi^⚠Experimental

Generates the WFI instruction